
2004 Microchip Technology Inc.
DS30491C-page 179
PIC18F6585/8585/6680/8680
FIGURE 16-4:
PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
Period
00
10
01
11
SIGNAL
PR2 + 1
CCP1CON
<7:6>
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Duty
Cycle
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1)
Note 1:
Relationships:
Period = 4 * TOSC * (PR2 + 1) * (TMR2 prescale value)
Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 prescale value)
Delay = 4 * TOSC * (PWM1CON<6:0>)